1. Field of the Invention
The present invention relates to a contactless nonvolatile semiconductor memory device.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a flash electrically-erasable programmable read-only memory (EEPROM) or an electrically programmable read-only memory (EPROM), the integration has been advanced by constructing bit lines as buried impurity diffusion layers.
In a prior art contactless nonvolatile semiconductor memory device, buried impurity diffusion layers as bit lines are formed beneath thick insulating layers (see J. Esquivel et al., "High Density Contactless, Self-aligned EPROM Cell Array Technology", IEDM Technical Digest, pp. 592-595, 1986). This will be explained later in detail.
In the above-mentioned prior art contactless nonvolatile semiconductor memory device, however, when the integration is advanced so that a spacing between the buried impurity diffusion layers becomes narrow, leakage currents flowing therebetween are increased, which invites a malfunction of nonvolatile memory cells. Also, this creates a serious short channel effect.
In addition, when patterning floating gate electrodes by a dry etching process, the buried impurity diffusion layers are also etched. As a result, the resistance of the buried impurity diffusion layers is increased, which reduces the read operation speed of the device.